1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a technique directed to simplifying the structure of a non-volatile semiconductor memory device and a process of fabricating the same.
2. Description of the Related Art
Flash memory, which is one type of semiconductor memories, is an electrically programmable and erasable ROM, and is also a non-volatile memory device widely used in portable phones, digital still cameras, and communications network equipment. Flash memory is mainly categorized into NOR type and NAND type. The NOR type flash memory is generally characterized in that it is randomly accessible and is faster for reading than the NAND type flash memory. There have been various proposals for schematic structures in the memory cell array in order to improve the performance of the NOR type flash memory (such as Japanese Patent Application Publication No. 2002-100689).
FIGS. 1A through 1C schematically show the structure of a conventional NOR type flash memory. More particularly, FIG. 1A is a top view of a part of the flash memory, FIG. 1B is a cross-sectional view taken along a line A-A′ shown in FIG. 1A, and FIG. 1C shows gate lines in the vicinity of a source contact.
Referring to these figures, a plurality of diffused regions (active regions) 18 are formed on a main surface of a silicon semiconductor substrate 10, and run in the longitudinal direction (Y direction). In FIGS. 1A and 1C, the diffused regions 18 are schematically depicted. The diffused regions 18 are spaced apart from each other in the transverse direction (X direction). Drain regions 11 are periodically formed in the diffused regions 18. The regions indicated by the reference numerals 18 are also bit lines, which are wiring layers obtained by patterning a metal such as aluminum. The bit lines 18 are electrically connected to the drain regions 11 via drain contacts 15.
A plurality of word lines (gate lines) 17 are formed on'the semiconductor substrate 10 and run in the transverse direction (X direction). The word lines 17 include gate electrodes 13. Below the gate electrodes 13, there are provided floating gates 20 formed on a tunnel oxide film on the semiconductor substrate, and insulation films 21 of ONO (oxide-nitride-oxide) formed on the floating gates 20. The gate electrodes 13 are provided on the insulation films 21.
Source regions, which run in the transverse direction as shown by arrow 14, are provided between word lines 17 adjacent to each other in the longitudinal direction. As shown in FIG. 1B, the source regions 12 are diffused regions formed in the surface of the semiconductor substrate 10. The source regions 12 are set at a reference potential Vss (for example, ground potential), and may be called Vss lines. A source line 19, which runs in the longitudinal direction of the semiconductor substrate 10, is formed every so many multiple bit lines 18 (for example, every eighth or sixteenth bit lines). The source line 19 is a wiring layer obtained by patterning a metal of, for example, aluminum into a given shape. The source line 19 is electrically connected to the source regions 12 via source contacts 16.
However, the NOR type flash memory as shown in FIGS. 1A through 1C has the following problems.
Firstly, the gate lines 17 are required to be curved in the vicinity of the source contacts 16 in order to secure spaces for forming the source contacts 16.
Secondly, the drain contacts 15 and the source contacts 16 have geometrically different arrangements on the top view (FIG. 1A) in order to secure the spaces for forming the source contacts 16. Assuming that the pitches of the contacts 15 and 16 in the Y direction are denoted as L, the source contacts 16 and the drain contacts 15 have a positional difference equal to a ½ pitch (L/2).
Thirdly, as shown in FIG. 1C, a condition C<D must be essentially satisfied where C denotes the pitch at which the wiring layers 18 connecting the drain contacts 15 are periodically arranged, and D denotes the pitch at which the wiring layers 19 connecting the source contacts 16 are periodically arranged. This results in a dead space in the vicinity of each source contact 16.
Fourthly, the diameter d1 of the source contact 16, the diameter d2 of the source contact 15′ adjacent to the source contact 16, and the diameters d3 of the other drain contacts 15 are mutually different from one another (d1>d2>d3), and may have mutually different shapes. It is thus necessary to obtain data about OPC (Optimum write Power Control) for each contact.